1. Field of the Invention
This invention relates in general to a method of fabricating a semiconductor device, and more specifically relates to a method of fabricating a metal-oxide semiconductor (MOS) transistor.
2. Description of Related Art
The fundamental structure of a MOS comprises a gate, a source and a drain regions in a substrate, wherein the gate further comprises a conductive layer and a gate oxide layer. Generally speaking, the material of conductive layer is polysilicon, which is the same as silicon in nature, and that of the gate oxide layer is SiO.sub.2. The source/drain regions are located in the substrate on opposite sides of the gate.
FIGS. 1A-1B illustrate steps in a process for forming a MOS transistor by a prior art method. Referring FIG. 1A, a substrate 10 is provided. Then a field oxide 12, is formed using the local oxidation of silicon (LOCOS) to define an active region 14. An oxide layer is deposited by thermal oxidation method to form a gate oxide layer. A polysilicon layer is deposited by low-pressure chemical vapor deposition (LPCVD), and the polysilicon layer is doped to enhance the conductivity of the polysilicon layer. Thereafter, the oxide layer and polysilicon layer are patterned to form the gate oxide layer 16 and polysilicon layer 18, resulting in the formation of the gate electrode 20.
Referring to FIG. 1B, lightly doped source/drain regions are formed in the substrate 10 by ion implanting the substrate 10 with a lower concentration dopant in a self-aligned process using the gate electrode 20 and the field oxide layer 12 as a mask. An oxide layer is formed and the oxide layer is anisotropically etched back to form spacers 24 on the sidewalls of gate electrode 20. Heavily doped source/drain regions 26 are formed in the substrate 10 by ion implanting higher concentrations of dopant into the substrate 10 using field oxide layer 12, gate electrode 20 and spacers 24 as a mask. A channel region 28 is formed under the gate oxide layer 16 and between the lightly doped source/drain regions 22. Follow-up steps, such as an annealing process, are performed to activate the dopants. However, those steps are well known to persons skilled in this art, so no detailed description thereof is needed here.
From a microscopic point of view, the polysilicon layer 18 of gate electrode 20 is a pure silicon material which is composed of single crystals of silicon grains with different crystal orientations, and there are grain boundaries between each single crystal of the silicon grains. Since there are several kinds of line defects and point defects in the grain boundaries, the diffusion ability of dopants through the grain boundaries is better than that diffusing though the interior grains. Therefore, the conductivity of the polysilicon layer can be changed via the doping process.
However, the disadvantage of producing a MOS transistor according to the prior art method is the formation of a leakage current. The polysilicon layer 18 of the gate electrode 20 undergoes one doping step. The dopants, which are used to form the source/drain regions 26 in the ion implantation step and the polysilicon layer in the doping step, penetrate into the channel region 28 through the grain boundaries of polysilicon layer. Moreover, those dopants also diffuse in the annealing step into the channel region 28 through the grain boundaries of polysilicon layer. These two effects cause leakage current.